1. Field of the Invention
This invention generally relates to digital processing devices and, more particularly, to a system and method for managing communications between processors.
2. Description of the Related Art
FIG. 1 is a schematic diagram depicting a processor employing buffer descriptor rings (prior art). Conventionally, communication between masters (e.g. processors and coprocessors) within a general purpose processor is enabled through the use of buffer descriptor rings. Shown is a processor with regular expressions (reg ex), security, and Ethernet buffer descriptor (BD) rings. A separate ring structure is provided for each to enable a one-to-one communication path within the system-on-chip (SoC). Each ring has a set of buffer descriptors and control mechanisms dedicated to the communication path between one producer (source processor) and one consumer (destination processor). Extensive software overhead is required to manage this communication. The additional requirement of multiple sources supporting differentiated flows accessing common coprocessors significantly complicates this communication, which can have a substantial impact on processor performance.
FIG. 2 is a diagram depicting a fixed link communication path with an Ethernet coprocessor (prior art). As an alternative to buffer descriptor rings, communication between processors and coprocessors within a network processor may utilize fixed links between different processing stages. This approach is targeted for high performance communication between stages within a fixed processing flow. However, fixed links are inflexible to new requirements and new flows. Congestion awareness is limited to next hop availability only (blocking).
Both of the above-references processor communication mechanisms are ill suited to next generation processor devices where increased throughput requires multiple processors and an increasing use of coprocessors for functions such as security. The use of multiple processors increases the complexity and the size of the communication load within a SoC.
Neither do conventional processor communications enable strict communication channels between specific producers and consumers, as control and data do not follow fixed predefined paths through the device. Flexibility is required as multiple processors communicate with each other and to/from common coprocessors. Further, differentiated paths within communication links are essential to meet the requirements of emerging multi-play services.
It would be advantageous if a processor communications system could provide hardware acceleration for communication within a SoC and between SoCs based upon a message passing paradigm. This message passing paradigm would enable an efficient, flexible, high performance communication infrastructure with built-in support for differentiated services, such as multi-play.